1. Field of the Invention
The embodiments described herein are directed to methods for fabricating non-volatile memory devices, and more particularly to methods for fabricating floating gate memory devices.
2. Background of the Invention
Current applications for non-volatile memory devices require that the devices be smaller, yet at the same time comprise higher densities. To meet these demands, memory cell sizes must get smaller. For example, it is well known to use virtual ground array designs in order to reduce the cell size for floating gate memory cells and non-volatile memory products, such as flash memory products. In general, however, a smaller cell size leads to smaller buried diffusion sizes, which are not necessarily compatible with conventional processing techniques and can lead to other problems.
For example, one problem that can occur as a result of the reduced buried diffusion sizes when using a conventional fabrication technique is a reduced gate coupling ratio (GCR) between the control gate and floating gate. Sufficient coupling is of course required in order to ensure that an adequate field is present in order to induce carriers to pass through the tunnel oxide layer onto the floating gate.
FIG. 1 is a schematic representation of a conventional floating gate memory cell 100. Memory cell 100 comprises a substrate 102 with diffusion regions 104 and 106 formed therein. For example, substrate 102 can be a P-type substrate and diffusion regions 104 and 106 can be N-type diffusion regions. In other embodiments, cell 100 can comprise an N-type substrate 102 with P-type diffusion regions 104 and 106. Although it will be understood that a P-type substrate is generally preferred.
Cell 100 further comprises a gate dielectric layer, sometimes referred to as a tunnel dielectric layer, 108 formed over substrate 102 between diffusion regions 104 and 106. A floating gate 110 is then formed over gate dielectric 108. Floating gate 110 is typically formed from a polysilicon. An inter-polysilicon (poly) dielectric layer 112 then separates floating gate 110 from a control gate 114. Control gate 114 is also typically formed from polysilicon. Inter-poly dielectric layer 112 can be formed from, e.g., a silicon dioxide (SiO2) material. In other embodiments, inter-poly dielectric 112 can comprise a multi-layer structure such as a Oxide-Nitride-Oxide (ONO) structure.
In operation, a high voltage is applied to control gate 114 in order to program cell 100. This voltage is coupled with floating gate 110 via a control gate capacitance (CCG). The coupled voltage causes an inversion channel to be formed in the upper layer of substrate 102 between diffusion regions 104 and 106. Voltages are then applied to diffusion regions 104 and 106 so as to create a large lateral electric field that will cause carriers to flow through the channel, e.g., from diffusion region 104 towards diffusion region 106.
The voltage coupled with floating gate 110 will create an electric field sufficient to cause some of the carriers to tunnel through tunnel dielectric 108 into floating gate 110. In other words, the voltage coupled with floating gate 110 needs to be capable of producing an electric field that can supply the carriers with enough energy to allow them to overcome the barrier height of gate dielectric 108. Accordingly, as mentioned above, sufficient coupling between control gate 114 and floating gate 110 is required in order to ensure that an adequate field is present to induce carriers to pass through tunnel dielectric 108 into floating gate 110.
It is important, therefore, to maintain adequate GCR in virtual ground arrays. As is understood, the GCR is a function of the CGC as well as the Source Capacitance (CS), Bulk Capacitance (CB), and Drain Capacitance (CD) illustrated in FIG. 1. The relationship is defined as:GCR=CCG/(CS+CB+CD+CCG)
Accordingly, the GCR can be increased by increasing CCG, which can be increased by increasing the area of overlap between the floating gate and the control gate. Stated another way, the GCR can be increased by increasing the surface area of inter-poly dielectric layer 112 between the control gate and the floating gate. As can be seen in FIG. 2, which illustrated a cross sectional view of a portion of a conventional floating gate memory device 200, an increased inter-poly area is conventionally achieved by including what is called a fourth poly layer 216.
Device 200 comprises a substrate 202 with diffusion regions 204, 206, and 208 formed therein. Each cell in device 200 then comprises a gate structure formed over substrate 202 and buried diffusion oxide structures 210 in contact with diffusion regions 204, 206, and 208. Each gate structure comprises a gate dielectric layer 212 and a floating gate structure formed from a first poly layer 214 and a fourth poly layer 216. Each gate structure also comprises an inter-poly layer 218 and a control gate structure formed from a second poly layer 220.
Thus, each gate structure is formed by depositing a dielectric layer 212 and a polysilicon layer 214 on substrate 202. A silicon nitride layer is then typically formed over polysilicon layer 214. The layers are then patterned using photolithography techniques and etched accordingly. After the buried diffusion oxide structures 210 are formed, another polysilicon layer, i.e., fourth poly layer 216, is formed over polysilicon layer 214. Fourth poly layer 214 is then patterned and etched to form the structure illustrated in FIG. 2. Inter-poly dielectric layer 218 is then formed over fourth poly layer 216.
By including fourth poly layer 216, the surface area of inter-poly dielectric layer 218 between the fourth poly layer 216 and the second poly layer 220 can be increased, which increases the GCR. Unfortunately, including fourth poly layer 216 increases the complexity of the process because it requires additional photolithographic steps, which are costly and can be difficult to implement due to alignment issues.